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XO

or

2 LVCMOS

or

Differential

Input

MUX

MUX

Divider M

225

Divider M

9

MUX

Divider M

375

PFD

Filter

VCO

PFD

Filter

VCO

Divider N

2048

Divider N

40

Divider N

3136

SO/AO/CLK_SEL

S1/A1

SCLOCK

Output Switch Matrix

PLL Bypass

60 MHZ (SSC on)

(DSP)

LV

CMOS

LV

CMOS

60 MHz (SSC off

(DSP)

30.72 MHz

(3G Baseband)

LV

CMOS

LV

CMOS

122.88 MHz

(3G RF Card))

27 MHz

(Video)

LV

CMOS

LV

CMOS

EEPROM

LOGIC

22.5792 MHz

(Audio)

PFD

Filter

VCO

SDATA

P0−Div

2

P1−Div

8

P2−Div

2

P3−Div

2

P4−Div

10

P5−Div

1

CLK_IN0

CLK_IN1

27 MHz

Crystal

SSC

SMBus

Y5

Y4

Y3

Y2

Y1

Y0

PLL3

PLL1

PLL2

w/SSC

fout +

fin

N

M

P

, i.e. fout +

27 MHz

3136

(375

10)

+ 22.5792 MHz

(1)

CDCE906

SCAS814 – NOVEMBER 2005

NOTE: All outputs are enabled and in non-inverting mode. S0, S1, and SSC comply according the default setting described in

Byte 10 and Byte 25 respectively.

Figure 8. Default Device Setting

The output frequency can be calculated:

13