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ADF7030 데이터시트(PDF) 24 Page - Analog Devices |
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ADF7030 데이터시트(HTML) 24 Page - Analog Devices |
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24 / 24 page ![]() ADF7030 Data Sheet OUTLINE DIMENSIONS 0.50 BSC BOTTOM VIEW TOP VIEW PIN 1 INDICATOR EXPOSED PAD PIN 1 INDICATOR SEATING PLANE 0.05 MAX 0.02 NOM 0.20 REF COPLANARITY 0.08 0.30 0.25 0.18 6.10 6.00 SQ 5.90 0.80 0.75 0.70 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.45 0.40 0.35 0.25 MIN 4.60 4.50 SQ 4.40 COMPLIANT TO JEDEC STANDARDS MO-220-WJJD. 40 1 11 10 20 21 30 31 Figure 41. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 6 mm × 6 mm Body, Very Very Thin Quad (CP-40-17) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADF7030BCPZN −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-40-17 ADF7030BCPZN-RL −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-40-17 EVAl-ADF7030DB7Z Evaluation Board (RF Daughter Board) EVAL-ADF7XXXMB4Z Evaluation Board (Motherboard) 1 Z = RoHS Compliant Part. ©2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11299-0-7/15(0) Rev. 0 | Page 24 of 24 |
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