ADMV7420 datasheet(21/25 Pages) AD

21 / 25 page

Data Sheet

ADMV7420

Rev.

A | Page 21 of 25

THEORY OF OPERATION

The ADMV7420 is a fully integrated SiP, I/Q low noise

downconverter that consists of two functional blocks.

The RFIN port of the ADMV7420 is connected to the gallium

arsenide (GaAs), low noise amplifier that consists of four stages

of low noise amplification that feed into the second block.

The second block is a GaAs, I/Q downconverter with an

integrated LO buffer and 6× multiplier. The 6× multiplier

allows the use of a lower frequency range LO input signal,

typically between 13.2 GHz and 14.6 GHz. The 6× multiplier is

implemented using a cascade of 3× and 2× multipliers. The LO

buffer amplifiers are included on chip to allow a typical LO

drive level of 4 dBm for typical performance. The LO path feeds

a quadrature splitter followed by on-chip baluns that drive the I

and Q mixer cores. The mixer cores comprise singly balanced

passive mixers. The RF input of the I and Q mixers are then

driven through an on-chip Wilkinson power splitter, which is

then fed by the first block of the ADMV7420.

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