| 전자부품 데이터시트 검색엔진 |
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L6986I 데이터시트(PDF) 26 Page - STMicroelectronics |
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L6986I 데이터시트(HTML) 26 Page - STMicroelectronics |
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26 / 60 page ![]() 5.5 Compensation network design The maximum bandwidth of the system can be designed up to fSW/6 up to 150 kHz maximum to guarantee a valid small signal model RC= 2∙π∙BW∙COUT∙VOUT 0.85V∙gCS∙gm_typ (20) where: fPOLE= ωP2∙π (21) ωP is defined by eq. (9) , gCS represents the current sense transconductance and gm TYP the error amplifier transconductance. CC= 52∙π∙RC∙BW (22) Example 1: VIN = 12 V, VOUT_pri = 5.3 V, ROUT_pri = 5.6 Ω (corresponding to almost 1 A load). Selecting the L6986I with VOUT_pri = 5.3 V, fSW = 500 kHz, Lpri = 18 µH, COUT_pri = 10 µF and ESR = 3 mΩ, RC = 56 kΩ, CC = 680 pF, CP = 4.7 pF (please refer to Table 11), the gain and phase bode diagrams are plotted respectively in Figure 29 and Figure 30. Figure 29. Bode plote (magnitude) Figure 30. Bode plot (phase) L6986I Compensation network design DS13647 - Rev 1 page 26/60 |
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