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L9026 데이터시트(PDF) 41 Page - STMicroelectronics |
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L9026 데이터시트(HTML) 41 Page - STMicroelectronics |
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41 / 60 page ![]() 11.6 SPI register 11.6.1 Register structure CHIP_ID Register name: CHIP_ID Address: Global Base Address + 0x00 Description: Chip ID register Field name Type Bit Offset Bit Width Reset Value Reset Sources Description CHIP_ID RO 0 8 AA Bit 0->7 00100010 BA Bit 0->7 00101010 BB Bit 0->7 01010101 X 8 bit chip identifier CFG_0 Register name: CFG_0 Address: Global Base Address + 0x01 Description: Configuration 0 Field name Type Bit Offset Bit Width Reset Value Reset Sources Description OUTn RW 2 6 0x00 POR_N, NRES pin, CFG_1.RST bit, VDD_UV Channel [7:2], MSB refers to channel 7 0: (default) OUTn low side 1: OUTn high side DIS_EN RW 1 1 0x00 POR_N, NRES pin, CFG_1.RST bit, VDD_UV 0: (default) DIS pin masked 1: DIS pin not masked NRES_EN RW 0 1 0x00 POR_N, NRES pin, CFG_1.RST bit, VDD_UV 0: (default) NRES pin masked 1: NRES pin not masked CFG_1 Register name: CFG_1 Address: Global Base Address + 0x02 Description: Configuration 1 Field name Type Bit Offset Bit Width Reset Value Reset Sources Description RST WO 7 1 0x00 POR_N, NRES pin, CFG_1.RST bit, VDD_UV Reset 0: (default) Normal operation 1: Execute Reset command (self clearing) ACT RW 6 1 0x00 POR_N, NRES pin, CFG_1.RST bit, VDD_UV active mode 0: (default) Normal operation or device leaves Active Mode 1: device enters and hold in Active Mode NU RO 2 4 0x00 X - L9026 SPI register DS13397 - Rev 5 page 41/60 |
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