List of figures

Figure 1.

Block diagram fixed version ........................................................... 2

Figure 2.

Block diagram adjustable version ....................................................... 2

Figure 3.

Pin connection (top view) ............................................................. 3

Figure 4.

Typical application for fixed version ...................................................... 4

Figure 5.

Typical application for adjustable version .................................................. 4

Figure 6.

VIN drop vs temperature.............................................................. 9

Figure 7.

UVLO vs temperature ............................................................... 9

Figure 8.

VOUT vs temperature (VBIAS@3 V, VIN@VOUT +0.3 V@1 mA) ................................... 9

Figure 9.

VOUT vs temperature (VBIAS@3 V, VIN@VOUT +0.3 V@1 A) .................................... 9

Figure 10.

Vin_line vs temp. (VOUT(NOM) + 0.3 V ≤ VIN ≤ 5.0 V) ........................................... 9

Figure 11.

VBIAS_line vs temp. (3.0 V or VOUT(NOM) + 1.6 V, whichever is greater, ≤ VBIAS ≤ 5.5 V) .................. 9

Figure 12.

Load vs temperature ............................................................... 10

Figure 13.

ISENSE vs temperature .............................................................. 10

Figure 14.

IBIAS vs temperature ............................................................... 10

Figure 15.

Enable high vs temperature (VBIAS min.) ................................................. 10

Figure 16.

IENABLE vs temperature ............................................................. 10

Figure 17.

Ground pin current vs load current ..................................................... 10

Figure 18.

Input voltage turn-on (VIN= from 0 V to 0.8 V, VBIAS=3 V, VEN=0.8 V, IOUT=1 A) ...................... 11

Figure 19.

Load transient (VIN=0.8 V, VBIAS=3 V, VEN=1 V, IOUT from 1 mA to 1 A) ............................ 11

Figure 20.

Line transient vs input voltage (VIN= from 0.8 V to 1.08 V, VBIAS=3 V, VEN=1 V, IOUT 100 mA)............. 11

Figure 21.

Line transient vs BIAS voltage (VIN=0.8 V to 1.08 V, VBIAS= from 2.8 to 3.8 V, VEN=1 V, IOUT=100 mA) ...... 11

Figure 22.

VBIAS PSRR vs frequency ........................................................... 11

Figure 23.

VIN PSRR vs frequency ............................................................ 11

Figure 24.

Output voltage spectral noise density vs frequency (VOUT= 1 V adj.) .............................. 12

Figure 25.

Output voltage spectral noise density vs frequency .......................................... 12

Figure 26.

Discharge_RMOS vs temperature ...................................................... 12

Figure 27.

Flip Chip6 (0.8x1.2 mm) package outline ................................................. 13

Figure 28.

Flip Chip6 (0.8x1.2 mm) recommended footprint ............................................ 14

Figure 29.

Flip Chip6 (0.8x1.2 mm) carrier tape outline ............................................... 15

LD57100

List of figures

DS13123 - Rev 5

page 20/21