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M50FLW040A 데이터시트(PDF) 46 Page - STMicroelectronics |
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M50FLW040A 데이터시트(HTML) 46 Page - STMicroelectronics |
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46 / 52 page ![]() M50FLW040A, M50FLW040B 46/52 Figure 24. Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only) Note: 1. A Status check of SR3 (VPP invalid) and SR4 (Program Error) can be made after each Program operation by following the correct command sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Address1, Address 2, Address 3 and Address 4 must be consecutive addresses differing only for address bits A0 and A1. AI08437B Write Address 4 & Data 4 (3) Read Status Register YES NO SR7 = 1 YES NO SR3 = 0 NO SR4 = 0 VPP Invalid Error (1, 2) Program Error (1, 2) Quadruple Byte Program command: – write 30h – write Address 1 & Data 1 (3) – write Address 2 & Data 2 (3) – write Address 3 & Data 3 (3) – write Address 4 & Data 4 (3) (memory enters read status state after the Quadruple Byte Program command) do: – Read Status Register – If SR7=0 and a Program/Erase Suspend command has been executed – SR7 is set to 1 – Enter suspend program loop If SR3 = 1, VPP invalid error: – error handler If SR4 = 1, Program error: – error handler End YES Suspend Suspend Loop NO YES Write 30h Start Write Address 1 & Data 1 (3) Write Address 2 & Data 2 (3) Write Address 3 & Data 3 (3) |
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