MCP48FVB21 datasheet(51/84 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS20005466A-page 51

MCP48FVBXX

7.0

SPI COMMANDS

This section documents the commands that the device

supports.

The MCP48FVBXX’s SPI command format supports

32 memory address locations and two commands.

The two commands are:

• Write command (C1:C0 = ‘00’)

• Read command (C1:C0 = ‘11’)

The supported commands are shown in Table 7-1. These

commands allow for both single data or continuous data

operation. Table 7-1 also shows the required number of

bit clocks for each command’s different mode of

operation.

The 24-bit commands (see Figure 7-1) are used to

read and write to the device registers (Read

Command and Write Command). These commands

contain a Command Byte and two Data Bytes.

Table 7-2 shows an overview of all the SPI commands

and their interaction with other device features.

TABLE 7-1:

SPI COMMANDS - NUMBER OF CLOCKS

Command

# of Bit

Clocks (1)

Data Update Rate

(8-bit/10-bit/12-bit)

(Data Words/Second)

Comments

Operation

Code

Mode

1MHz

10 MHz

20 MHz

Write Command

No (2) Single

41,666

416,666

833,333

No (2) Continuous

 n

41,666

416,666

833,333

For 10 data words

Read Command

No (2) Single

41,666

416,666

N.A.

No (2) Continuous

 n

41,666

416,666

N.A.

For 10 data words

Note 1:

“n” indicates the number of times the command operation is to be repeated.

If the state of the HVC pin is VIHH, then the command is ignored, but a Command Error condition

(CMDERR) will NOT be generated.

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