MCP47FVB11 datasheet(31/84 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS20005466A-page 31

MCP48FVBXX

4.2

Device Memory

User memory includes two types of memory:

• Volatile Register Memory (RAM)

• Device Configuration Memory

Each memory address is 16 bits wide.The memory

mapped register space is shown in Table 4-1. (see

Section 4.2.2, “Device Configuration Memory”

4.2.1

VOLATILE REGISTER MEMORY

(RAM)

There are up to five volatile memory locations:

• DAC0 and DAC1 Output Value Registers

•VREF Select Register

• Power-Down Configuration Register

• Gain and Status Register

The volatile memory starts functioning when the

device VDD is at (or above) the RAM retention voltage

(VRAM). The volatile memory will be loaded with the

default device values when the VDD rises across the

VPOR/VBOR voltage trip point.

TABLE 4-1:

MEMORY MAP (X16)

Function

00h

Volatile DAC0 Register

10h

Reserved (1, 2)

01h

Volatile DAC1 Register

11h

Reserved (1, 2)

02h

Reserved (1)

12h

Reserved (1, 2)

03h

Reserved (1)

13h

Reserved (1, 2)

04h

Reserved (1)

14h

Reserved (1, 2)

05h

Reserved (1)

15h

Reserved (1, 2)

06h

Reserved (1)

16h

Reserved (1, 2)

07h

Reserved (1)

17h

Reserved (1, 2)

08h

VREF Register

18h

Reserved (1, 2)

09h

Power-Down Register

19h

Reserved (1, 2)

0Ah

Gain and Status Register

1Ah

Reserved (1, 2)

0Bh

Reserved (1)

1Bh

Reserved (1, 2)

0Ch

Reserved (1)

1Ch

Reserved (1, 2)

0Dh

Reserved (1)

1Dh

Reserved (1, 2)

0Eh

Reserved (1)

1Eh

Reserved (1, 2)

0Fh

Reserved (1)

1Fh

Reserved (1, 2)

Volatile Memory address range

Nonvolatile Memory address range

Note 1:

Reading a reserved memory location will result in the SPI command Command Error condition. The SDO

pin will output all ‘0’s. Forcing the CS pin to the VIH state will reset the SPI interface.

Nonvolatile memory address range is shown to reflect memory map compatibility with the MCP48FEBXX

family of devices.

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