PIMXRT516SCVL2A datasheet(35/124 Pages) NXP

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Electrical characteristics

i.MX RT1160 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 04/2021

NXP Semiconductors

4.2.3.1

LDO_SNVS_ANA

Table 16 shows the parameters of LDO_SNVS_ANA.

4.2.3.2

LDO_SNVS_DIG

Table 17 shows the parameters of LDO_SNVS_DIG.

4.2.3.3

LDO_PLL

Table 18 shows the parameters of LDO_PLL.

4.2.3.4

LPSR_LDO_DIG

LPSR_LDO_DIG provides 1.0 V power source (VDD_LPSR_DIG) from 1.8V power domain

(VDD_LPSR_ANA). The trim voltage range of LDO output is from 0.7 V to 1.15 V. There are two work

modes: Low Power mode and High Power mode. In typical PVT case, the static current consumption is

less than 3 A in Low Power mode. The maximum drive strength of this LDO regulator is 50 mA in High

Power mode.

Table 16. LDO_SNVS_ANA specification

Specification

Min

Typ

Max

Unit

VDD_SNVS_IN

2.4

3.6

VDD_SNVS_ANA

1.65

1.75

1.95

I_out

—

External decoupling capacitor

—

2.2

—

F

Table 17. LDO_SNVS_DIG specification

Specification

Min

Typ

Max

Unit

VDD_SNVS_ANA

1.65

1.75

1.95

VDD_SNVS_DIG

0.65

0.85

0.95

I_out

—

External decoupling capacitor

—

0.22

—

F

Table 18. LDO_PLL specification

Specification

Min

Typ

Max

Unit

VDDA_1P8_IN

1.71

1.8

1.89

VDDA_1P0

0.9

1.2

I_out

—

External decoupling capacitor

—

2.2

—

F

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