MCP3461 datasheet(39/108 Pages) MICROCHIP

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DS20006180D-page 39

MCP3461/2/4

FIGURE 5-5:

One-Shot Mode vs. Continuous Mode.

Since the converter is effectively doing two conversions

when the AZ_MUX bit is enabled, the conversion time

is equal to 2 x TCONV in this mode. As described in

Section 5.1.3 “ADC Offset Cancellation Algorithm”,

this selection is not compatible with the Continuous

Conversion mode, therefore, the output data rate is

equal to 1/(2 x TCONV) in this mode.

Table 5-6 summarizes the possible filter settings and

their associated Conversion Time, TCONV, as well as

their output data rate (DRCLK) in Continuous mode.

When OSR is larger than 20480 for typical master clock

frequency, MCLK = 4.9152 MHz, the device includes an

additional 50/60 Hz rejection by aligning decimation filter

notches with a multiple of 50 or 60 Hz depending on the

OSR setting. The rejection band depends strongly on

the master clock accuracy and corresponds to a

first-order decimation filter rejection rate.

The high OSR settings can be used for applications

requiring very low noise and slow data rates.

Figure 5-6 shows the frequency response of the

decimation filter with default settings. Figure 5-7

represents the frequency response of the filter with the

highest OSR settings and a line rejection at 60 Hz.

TCONV

One-Shot mode

Conversions are Serialized,

Filter is Reset After Each

Conversion

Group Delay = TCONV

Data Rate: 1/(TCONV)

Conversion1

TCONV

Continuous mode

Conversions are Pipelined,

Filter is Never Reset

Group Delay : TCONV

Data Rate: DRCLK

TCONV

Conversion2

TCONV

Conversion3

1/DRCLK

TCONV

Analog Input

Signal

Conversion1

Conversion2

TCONV = Settling Time

IRQ

ADC

Status

ADC

Status

IRQ

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