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MCP3561T-E/ST 데이터시트(PDF) 82 Page - Microchip Technology

부품명 MCP3561T-E/ST
상세설명  Two/Four/Eight-Channel, 153.6 ksps, Low-Noise 24-Bit Delta-Sigma ADCs
PDF  108 Pages
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
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MCP3561T-E/ST 데이터시트(HTML) 82 Page - Microchip Technology

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MCP3561/2/4
DS20006181C-page 82
 2019-2021 Microchip Technology Inc.
8.1
ADCDATA Register
Name
Bits
Address
Cof
ADCDATA
4/24/32
0x0
R
REGISTER 8-1:
ADCDATA: ADC CHANNEL DATA OUTPUT REGISTER
R-0
ADCDATA[23:0]
bit 23
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 23-0
ADCDATA[23:0]: ADC Output Code
The data are post-calibration if the EN_OFFCAL or EN_GAINCAL bits are enabled. The data can be
formatted in 24/32-bit modes depending on the DATA_FORMAT[1:0] settings (see Section 5.6 “ADC
Output Data Format”).
The ADC Channel Data Output registers always contain the most recent A/D conversion data. The
register is updated at each data ready internal signal (it depends on the OSR and CONV_MODE
settings). The register is latched at the start of each SPI Read command. The register is double
buffered to avoid data loss. There is a small time delay, tDODR, after each data ready, where the user
has to wait for the data to be available. Otherwise, data corruption can occur (when the internal data
are refreshed).
When IRQ_MODE[1:0] = 1x, this register becomes a 4-bit wide register containing the MDAT output
codes, which are the outputs of the modulator that are represented by four comparator outputs
(COMP[3:0], see Section 5.4.2 “Modulator Output Block”).



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