MCP48FVB24 datasheet(53/112 Pages) MICROCHIP

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DS20006362A-page 53

MCP48FXBX4/8

4.0

GENERAL DESCRIPTION

The MCP48FXBX4 (MCP48FXB04, MCP48FXB14

and MCP48FXB24) devices are quad-channel voltage

output devices. The MCP48FXBX8 (MCP48FXB08,

MCP48FXB18 and MCP48FXB28) devices are

octal-channel voltage output devices.

These devices are offered with 8-bit (MCP48FXB0X),

10-bit (MCP48FXB1X) and 12-bit (MCP48FXB2X) res-

olutions and include nonvolatile memory (EEPROM),

an SPI serial interface and two write Latch pins (LAT0,

LAT1) to control the update of the written DAC value to

the DAC output pin.

The devices use a resistor ladder architecture. The

resistor ladder DAC is driven from a software-

selectable voltage reference source. The source can

be either the device’s internal VDD, an external VREF

pin voltage (buffered or unbuffered) or an internal band

gap voltage source.

The DAC output is buffered with a low-power and

precision output amplifier (op amp). This output

amplifier provides a rail-to-rail output with low offset

voltage and low noise. The gain (1x or 2x) of the

output buffer is software configurable.

This device family also has a user-programmable

nonvolatile memory (EEPROM) option, which allows

the user to save the desired POR/BOR value of the

DAC register and device Configuration bits.

High-voltage lock bits can be used to ensure that the

device’s output settings are not accidentally modified.

The device operates from a single-supply voltage. This

voltage is specified from 2.7V to 5.5V for full specified

operation and from 1.8V to 5.5V for digital operation.

The device can operate between 1.8V and 2.7V, but its

analog performance is significantly reduced; therefore,

most device parameters are not specified for this

range.

The main functional blocks are:

• Power-on Reset/Brown-out Reset (POR/BOR)

• Device Memory

• Resistor Ladder

• Output Buffer/VOUT Operation

• Internal Band Gap

• SPI Serial Interface Module

4.1

Power-on Reset/Brown-out Reset

(POR/BOR)

The internal POR/BOR circuit monitors the power

supply voltage (VDD) during operation. This circuit

ensures correct device start-up at system power-up

and power-down events. The device’s RAM Retention

Voltage (VRAM) is lower than the POR/BOR Voltage

(VPOR/VBOR) trip point. The maximum VPOR/VBOR

voltage is less than 1.8V.

POR occurs as the voltage rises (typically from 0V),

while BOR occurs as the voltage falls (typically from

VDD(MIN) or higher).

The POR and BOR trip points are at the same voltage

and the condition is determined by whether the VDD

voltage is rising or falling (see Figure 4-1). What occurs

is different depending on whether the reset is a POR or

BOR.

When VPOR/VBOR < VDD < 2.7V, the electrical perfor-

mance may not meet the data sheet specifications. In

this region, the device is capable of reading and writing

to its EEPROM and reading and writing to its volatile

memory if the proper serial command is executed.

4.1.1

POWER-ON RESET

The Power-on Reset is the case where the VDD has

power applied to it, ramping up from the VSS voltage

level. As the device powers up, the VOUT pin floats to

an unknown value. When VDD is above the transistor

threshold voltage of the device, the output starts to be

pulled low. After the VDD is above the POR/BOR trip

point (VBOR/VPOR), the resistor network’s wiper is

loaded with the POR value (midscale). The volatile

memory determines the analog output (VOUT) pin volt-

age. After the device is powered up, the user can

update the device’s memory.

When the rising VDD voltage crosses the VPOR trip

point, the following occurs:

• The nonvolatile DAC register value is latched into

the volatile DAC register.

• The nonvolatile Configuration bit values are

latched into the volatile Configuration bits.

• The POR status bit is set (‘1’).

• The POR Reset Delay Timer (tPORD) starts; when

the POR Reset Delay Timer (tPORD) times out, the

serial interface is operational. During this delay

time, the serial interface will not accept commands.

• The Device Memory Address Pointer is forced to

00h.

The Analog Output (VOUT) state is determined by the

state of the volatile Configuration bits and the DAC

Figure 4-1 illustrates the conditions for power-up and

power-down events under typical conditions.

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