MCP48FVB18 datasheet(68/112 Pages) MICROCHIP

68 / 112 page

MCP48FXBX4/8

DS20006362A-page 68

 2020 Microchip Technology Inc.

5.4

Output Buffer/VOUT Operation

The output driver buffers the Wiper Voltage (VW) of the

resistor ladder.

The DAC output is buffered with a low-power and pre-

cision output amplifier (op amp). This amplifier provides

a rail-to-rail output with low offset voltage and low

noise. The amplifier’s output can drive the resistive and

high capacitive loads without oscillation. The amplifier

provides a maximum load current, which is enough for

most programmable voltage reference applications.

See Section 1.0 “Electrical Characteristics” for the

specifications of the output amplifier.

Figure 5-5 shows the block diagram of the output driver

circuit.

The user can select the output gain of the output

amplifier. The gain options are:

Gain of 1, when either the VDD, External VREF or

Band Gap mode are used. In case of the Band

Gap mode, the effective gain is 2; see

Section 5.3 “Internal Band Gap”.

Gain of 2, when the External VREF or Internal

Band Gap modes are used. In case of the Band

Gap mode, the effective gain is 4; see

Section 5.3 “Internal Band Gap”.

FIGURE 5-5:

Output Driver Block Diagram.

5.4.1

PROGRAMMABLE GAIN

The amplifier’s gain is controlled by the Gain (G)

Configuration bit (see Register 4-5) and the VRL

reference selection.

The volatile Gain bit value can be modified by:

• POR events

• BOR events

• SPI WRITE commands

5.4.2

OUTPUT VOLTAGE

The volatile DAC register values, along with the

device’s Configuration bits, control the analog VOUT

voltage. The volatile DAC register’s value is unsigned

binary. The formula for the output voltage is given in

Equation 5-2. Table 5-5 shows examples of volatile

DAC register values and the corresponding theoretical

VOUT voltage for the MCP48FXBX4/8 devices.

EQUATION 5-2:

CALCULATING OUTPUT

VOLTAGE (VOUT)

The following events update the DAC register value,

and therefore, the analog Voltage Output (VOUT):

•POR

•BOR

• WRITE command

The VOUT voltage starts driving to the new value after

the event has occurred.

5.4.3

STEP VOLTAGE (VS)

The step voltage depends on the device resolution and

the calculated output voltage range. One LSb is

defined as the ideal voltage difference between two

successive codes. The step voltage can be easily cal-

culated by using Equation 5-3 (DAC register value is

equal to 1). Theoretical step voltages are shown in

Table 5-2 for several VREF voltages.

EQUATION 5-3:

VS CALCULATION

Note:

The load resistance must be kept higher

than 5 k

 for the stable and expected

analog

output

(to

meet

electrical

specifications).

Gain

(1x or 2x)

VOUT

PDnB:PDnA

VDD

PDnB:PDnA

–

Note:

When Gain = 2 (VRL= VREF) and if

VREF > VDD/2, the VOUT voltage will be

limited to VDD. So if VREF = VDD, then the

VOUT voltage will not change for volatile

DAC register values midscale and

greater, since the op amp is at full-scale

output.

Where:

# Resistors in R-Ladder = 4096 (MCP48FXB2X)

1024 (MCP48FXB1X)

256 (MCP48FXB0X)

VOUT

VRL DAC Register Value



# Resistor in Resistor Ladder

----------------------------------------------------------------------Gain



Where:

# Resistors in R-Ladder = 4096 (12-bit)

1024 (10-bit)

256 (8-bit)

VRL

# Resistor in Resistor Ladder

----------------------------------------------------------------------Gain



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