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ACE24AC1024EDPTH 데이터시트(PDF) 6 Page - ACE Technology Co., LTD. |
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ACE24AC1024EDPTH 데이터시트(HTML) 6 Page - ACE Technology Co., LTD. |
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6 / 16 page ![]() ACE24AC1024E Two-wire Serial EEPROM VER 1.1 6 Write Operations (A) Byte Write A write operation requires the seventh bit of the device address (P0) and two 8-bit data word address following the device address word and acknowledge signal. Upon receipt of this address, the EEPROM will respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will again output a “0”. The addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters into an internally-timed write cycle state. All inputs are disabled during this write cycle and the EEPROM will not respond until the writing is completed (figure 3). (B) Page Write The 1024K EEPROM are capable of 256-byte page write. A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. The microcontroller can transmit up to 255 more data words after the EEPROM acknowledges receipt of the first data word. The EEPROM will respond with a “0” after each data word is received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 4). The lower 8 bits of the data word address are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. If more than 256 data words are transmitted to the EEPROM, the data word address will “roll over” and the previous data will be overwritten. (C) Acknowledge Polling Acknowledge polling may be used to poll the programming status during a self-timed internal programming. By issuing a valid read or write address command, the EEPROM will not acknowledge at the 9th clock cycle if the device is still in the self-timed programming mode. However, if the programming completes and the chip has returned to the standby mode, the device will return a valid acknowledge signal at the 9th clock cycle. |
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