CY29976
Document #: 38-07413 Rev. *A
Page 3 of 10
Description
The CY29976 has an integrated PLL that provides low-skew
and low-jitter clock outputs for high-performance microproces-
sors. Three independent banks of four outputs as well as an
independent PLL feedback output, FB_OUT, provide excep-
tional flexibility for possible output configurations. The PLL is
ensured stable operation given that the VCO is configured to
run between 200 MHz to 480 MHz. This allows a wide range
of output frequencies up to125 MHz.
The phase detector compares the input reference clock to the
external feedback input. For normal operation, the external
feedback input, FB_IN, is connected to the feedback output,
FB_OUT. The internal VCO is running at multiples of the input
reference clock set by FB_SEL(0:2) and VCO_SEL select in-
puts, refer to Frequency Table. The VCO frequency is then
divided down to provide the required output frequencies.
These dividers are set by SELA(0,1), SELB(0,1), SELC(0,1)
select inputs, see Table 2 below. For situations were the VCO
needs to run at relatively low frequencies and hence might not
be stable, assert VCO_SEL low to divide the VCO frequency
by 2. This will maintain the desired output relationships, but will
provide an enhanced PLL lock range.
The CY29976 is also capable of providing inverted output
clocks. When INV_CLK is asserted HIGH, QC2 and QC3 out-
put clocks are inverted. These clocks could be used as feed-
back outputs to the CY29976 or a second PLL device to gen-
erate early or late clocks for a specific design. This inversion
does not affect the output to output skew.
Table 2.
VCO_SEL
SELA1
SELA0
QA
SELB1
SELB0
QB
SELC1
SELC0
QC
0
0
0VCO/4
0
0
VCO/40
0
VCO/16
0
0
1
VCO/12
0
1
VCO/12
0
1
VCO/4
0
1
0VCO/8
1
0
VCO/81
0
VCO/12
0
1
1
VCO/24
1
1
VCO/20
1
1
VCO/8
1
0
0VCO/2
0
0
VCO/20
0VCO/8
1
0
1VCO/6
0
1
VCO/60
1VCO/2
1
1
0VCO/4
1
0
VCO/41
0VCO/6
1
1
1
VCO/12
1
1
VCO/10
1
1
VCO/4
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