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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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UPD16635 데이터시트(PDF) 13 Page - NEC |
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UPD16635 데이터시트(HTML) 13 Page - NEC |
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13 / 19 page  µPD16635 13 Conditions Required for Timing (TA = –10 to +75 °C, VDD1 = 3.3 V ±0.3 V, VSS1 = VSS2 = 0 V, tr = tf = 8.0 ns) Parameter Symbol Condition MIN. TYP. MAX. Unit Clock Pulse Width PWCLK 30 ns Clock Pulse Low Period PWCLK(L) 6ns Clock Pulse High Period PWCLK(H) 6ns Data Setup Time tSETUP1 6ns Data Hold Time tHOLD1 6ns Start Pulse Setup Time tSETUP2 6ns Start Pulse Hold Time tHOLD2 6ns Start Pulse Low Period tSPL 6ns STB Pulse Width PWSTB 1 µs Data Invalid Period tINV 1 CLK Final Data Timing tLDT 2 CLK CLK-STB Time tCLK-STB CLK ↑ → STB ↓ 6ns STB-CLK Time tSTB-CLK STB ↓ → CLK ↑ 6ns Time Between STB and tSTB-STH STB ↓ → STHR ↑ 60 ns Start Pulse POL-STB Time tPOL-STB POL ↑ or ↓ → STB ↑ –5 ns STB-POL Time tSTB-POL STB ↓ → POL ↑ or ↓ 6ns |
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