MPC755 datasheet(12/56 Pages) NXP

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MPC755 RISC Microprocessor Hardware Specifications, Rev. 8

Freescale Semiconductor

Electrical and Thermal Characteristics

4.2

AC Electrical Characteristics

This section provides the AC electrical characteristics for the MPC755. After fabrication, functional parts

are sorted by maximum processor core frequency as shown in Section 4.2.1, “Clock AC Specifications,”

and tested for conformance to the AC specifications for that frequency. The processor core frequency is

determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0:3] signals. Parts are sold

by maximum processor core frequency; see Section 10, “Ordering Information.”

4.2.1

Clock AC Specifications

Table 8 provides the clock AC timing specifications as defined in Figure 3.

Table 8. Clock AC Timing Specifications

At recommended operating conditions (see Table 3)

Characteristic

Symbol

Maximum Processor Core Frequency

Unit

Notes

300 MHz

350 MHz

400 MHz

Min

Max

Min

Max

Min

Max

Processor frequency

fcore

200

300

200

350

200

400

MHz

VCO frequency

fVCO

400

600

400

700

400

800

MHz

SYSCLK frequency

fSYSCLK

100

MHz

SYSCLK cycle time

tSYSCLK

SYSCLK rise and fall time

tKR, tKF

—2.0

tKR, tKF

—1.4

SYSCLK duty cycle measured at

OVDD/2

tKHKL/

tSYSCLK

SYSCLK jitter

—

±150

—

±150

—

±150

3, 4

Internal PLL relock time

—100

μs3, 5

Notes:

1. Caution: The SYSCLK frequency and PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK (bus)

frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating

frequencies. Refer to the PLL_CFG[0:3] signal description in Section 8.1, “PLL Configuration

,” for valid PLL_CFG[0:3]

settings.

2. Rise and fall times measurements are now specified in terms of slew rates, rather than time to account for selectable I/O bus

interface levels. The minimum slew rate of 1 V/ns is equivalent to a 2 ns maximum rise/fall time measured at 0.4 and 2.4 V

(OVDD = 3.3 V) or a rise/fall time of 1 ns measured at 0.4 and 1.8 V (OVDD = 2.5 V).

3. Timing is guaranteed by design and characterization.

4. This represents total input jitter—short term and long term combined—and is guaranteed by design.

5. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for PLL

lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also applies when

the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted

for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.

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