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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PIMXRT516SCVM5A 데이터시트(PDF) 95 Page - NXP Semiconductors |
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PIMXRT516SCVM5A 데이터시트(HTML) 95 Page - NXP Semiconductors |
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95 / 124 page  Electrical characteristics i.MX RT1160 Crossover Processors Data Sheet for Extended Industrial Products, Rev. 0, 04/2021 NXP Semiconductors 95 Figure 49. RGMII transmit signal timing diagram Figure 50. RGMII receive signal timing diagram TskewR 3 Data to clock input skew at receiver 1 2.6 ns Duty_G4 Duty cycle for Gigabit 45 85 % Duty_T4 Duty cycle for 10/100T 40 90 % Tr/Tf Rise/fall time (20–80%) — 0.98 ns 1 The timings assume the following configuration: DDR_SEL = (11)b DSE (drive-strength) = (111)b 2 For 10 Mbps and 100 Mbps, T cyc will scale to 400 ns ±40 ns and 40 ns ±4 ns respectively. 3 For all versions of RGMII prior to 2.0; this implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the associated clock signal. For 10/100, the Max value is unspecified. 4 Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain as long as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned between. Table 94. RGMII signal switching specifications1 (continued) Symbol Description Min. Max. Unit |
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