RF Monolithics, Inc.

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©1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.

TR3003-070105

threshold, or squelch, offsets the comparator’s slicing level from 0 to 90

mV, and is set with a resistor between the RREF and THLD1 pins. This

threshold allows a trade- off between receiver sensitivity and output noise

density in the no-signal condition. For best sensitivity, the threshold is set

to 0. In this case, noise is output continuously when no signal is present.

This, in turn, requires the circuit being driven by the RXDATA pin to be able

to process noise (and signals) continuously.

This can be a problem if RXDATA is driving a circuit that must “sleep” when

data is not present to conserve power, or when it its necessary to minimize

false interrupts to a multitasking processor. In this case, noise can be

greatly reduced by increasing the threshold level, but at the expense of

sensitivity. The best 3 dB bandwidth for the low-pass filter is also affected

by the threshold level setting of DS1. The bandwidth must be increased as

the threshold is increased to minimize data pulse-width variations with sig-

nal amplitude.

Data slicer DS2 can overcome this compromise once the signal level is

high enough to enable its operation. DS2 is a “dB-below- peak” slicer. The

peak detector charges rapidly to the peak value of each data pulse, and de-

cays slowly in between data pulses (1:1000 ratio). The slicer trip point can

be set from 0 to 120 mV below this peak value with a resistor between

RREF and THLD2. A threshold of 60 mV is the most common setting,

which equates to “6 dB below peak” when RFA1 and RFA2 are running a

50%-50% duty cycle. Slicing at the “6 dB-below-peak” point reduces the

signal amplitude to data pulse-width variation, allowing a lower 3 dB filter

bandwidth to be used for improved sensitivity.

DS2 is best for ASK modulation where the transmitted waveform has been

shaped to minimize signal bandwidth. However, DS2 is subject to being

temporarily “blinded” by strong noise pulses, which can cause burst data

errors. Note that DS1 is active when DS2 is used, as RXDATA is the logical

AND of the DS1 and DS2 outputs. DS2 can be disabled by leaving THLD2

disconnected. A non-zero DS1 threshold is required for proper AGC oper-

ation.

AGC Control

The output of the Peak Detector also provides an AGC Reset signal to the

AGC Control function through the AGC comparator. The purpose of the

AGC function is to extend the dynamic range of the receiver, so that the re-

ceiver can operate close to its transmitter when running ASK and/or high

data rate modulation. The onset of saturation in the output stage of RFA1

is detected and generates the AGC Set signal to the AGC Control function.

The AGC Control function then selects the 5 dB gain mode for RFA1. The

AGC Comparator will send a reset signal when the Peak Detector output

(multiplied by 0.8) falls below the threshold voltage for DS1.

A capacitor at the AGCCAP pin avoids AGC “chattering” during the time it

takes for the signal to propagate through the low-pass filter and charge the

peak detector. The AGC capacitor also allows the hold-in time to be set

longer than the peak detector decay time to avoid AGC chattering during

runs of “0” bits in the received data stream. Note that AGC operation re-

quires the peak detector to be functioning, even if DS2 is not being used.

AGC operation can be defeated by connecting the AGCCAP pin to Vcc.

The AGC can be latched on once engaged by connecting a 150 kilohm re-

sistor between the AGCCAP pin and ground in lieu of a capacitor.

Receiver Pulse Generator and RF Amplifier Bias

The receiver amplifier-sequence operation is controlled by the Pulse Gen-

erator & RF Amplifier Bias module, which in turn is controlled by the

PRATE and PWIDTH input pins, and the Power Down (sleep) Control Sig-

nal from the Bias Control function.

In the low data rate mode, the interval between the falling edge of one

a resistor between the PRATE pin and ground. The interval can be adjust-

ed between 0.1 and 5 µs. In the high data rate mode (selected at the

PWIDTH pin) the receiver RF amplifiers operate at a nominal 50%-50%

are controlled by the PRATE resistor over a range of 0.1 to 1.1 µs.

In the low data rate mode, the PWIDTH pin sets the width of the ON pulse

is set at 1.1 times the pulse width to RFA1 in the low data rate mode). The

when the PWIDTH pin is connected to Vcc through a 1 M resistor, the RF

amplifiers operate at a nominal 50%-50% duty cycle, facilitating high data

rate operation. In this case, the RF amplifiers are controlled by the PRATE

resistor as described above.

Both receiver RF amplifiers are turned off by the Power Down Control Sig-

nal, which is invoked in the sleep and transmit modes.

Transmitter Chain

The transmitter chain consists of a SAW delay line oscillator followed by a

modulated buffer amplifier. The SAW filter suppresses transmitter harmon-

ics to the antenna. Note that the same SAW devices used in the amplifier-

sequenced receiver are reused in the transmit modes.

Transmitter operation supports two modulation formats, on-off keyed

(OOK) modulation, and amplitude-shift keyed (ASK) modulation. When

OOK modulation is chosen, the transmitter output turns completely off be-

tween “1” data pulses. When ASK modulation is chosen, a “1” pulse is rep-

resented by a higher transmitted power level, and a “0” is represented by a

lower transmitted power level. OOK modulation provides compatibility with

first-generation ASH technology, and provides for power conservation.

ASK modulation must be used for high data rates (data pulses less than 30

µs). ASK modulation also reduces the effects of some types of interference

and allows the transmitted pulses to be shaped to control modulation band-

width.

The modulation format is chosen by the state of the CNTRL0 and the

CNTRL1 mode control pins, as discussed below. When either modulation

format is chosen, the receiver RF amplifiers are turned off. In the OOK

mode, the delay line oscillator amplifier TXA1 and buffer amplifier TXA2 are

turned off when the voltage to the TXMOD input falls below 220 mV. In the

OOK mode, the data rate is limited by the turn-on and turn-off times of the

delay line oscillator, which are 12 and 6 µs respectively. In the ASK mode

TXA1 is biased ON continuously, and the output of TXA2 is modulated by

the TXMOD input current. Minimum output power occurs in the ASK mode

when the modulation driver sinks about 10 µA of current from the TXMOD

pin.

The transmitter RF output power is proportional to the input current to the

TXMOD pin. A series resistor is used to adjust the peak transmitter output

power. 1.5 dBm of output power requires about 250 µA of input current.

Transceiver Mode Control

The four transceiver operating modes – receive, transmit ASK, transmit

OOK, and power-down (sleep), are controlled by the Modulation & Bias

Control function, and are selected with the CNTRL1 and CNTRL0 control

pins. Setting CNTRL1 and CNTRL0 both high place the unit in the receive

mode. Setting CNTRL1 high and CNTRL0 low place the unit in the ASK

transmit mode. Setting CNTRL1 low and CNTRL0 high place the unit in the

OOK transmit mode. Setting CNTRL1 and CNTRL0 both low place the unit

in the power-down (sleep) mode. Note that the resistor driving TXMOD

must be low in the receive and power-down modes. The PWIDTH resistor

must also be low in the power down mode to minimize current. CNTRL1

and CNTRL0 are CMOS compatible inputs. These inputs must be held at

a logic level; they cannot be left unconnected.