ACE25QC200GLTMTH datasheet(46/64 Pages) ACE

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ACE25QC200GL

2M BIT SPI NOR FLASH

VER 1.1

Program Security Registers (42h)

The Program Security Register instruction is similar to the Page Program instruction. It allows from one

byte to 512 bytes of security register data to be programmed by two times (one time program 256 bytes) at

previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device

will accept the Program Security Register Instruction (Status Register bit WEL= 1). The instruction is

initiated by driving the /CS pin low then shifting the instruction code “42h” followed by a 24- bit address

(A23-A0) and at least one data byte, into the SI pin. The /CS pin must be held low for the entire length of

the instruction while data is being sent to the device

Address

A23-16

A15-12

A11-9

A8-0

Security Registers 1

00H

0001

0000

Byte Address

Security Registers 2

00H

0010

0000

Byte Address

Security Registers 3

00H

0011

0000

Byte Address

The Program Security Register instruction sequence is shown in Figure36. The Security Register Lock Bits

(LB3-1) in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit is set to

1, the corresponding security register will be permanently locked, Program Security Register instruction to

that register will be ignored.

Figure36. Program Security Registers Instruction

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