SH7705 datasheet(13/739 Pages) RENESAS

13 / 739 page

Rev. 2.00, 09/03, page xiii of xlvi

Item

Page

Revisions (See Manual for Details)

7.13 Others

Reset

237

In standby, sleep, and manual reset, control registers of the

bus state controller are not initialized. At manual reset, the

current bus cycle being executed is completed and then the

access wait state is entered.

Since the RTCNT continues

counting up during manual reset signal assertion, a refresh

request occurs to initiate the refresh cycle.

Note that arbitration requests using

BREQ are not accepted

during manual reset signal assertion.

8.3.4 DMA Channel

Control Registers (CHCR)

244

Bits 15, 14 description amended

00: Fixed destination address

(setting prohibited in 16-byte transfer)

245

Bits 13, 12 description amended

00: Fixed source address

(setting prohibited in 16-byte transfer)

8.4.3 Channel Priority

Round-Robin Mode

258

⋅⋅⋅⋅⋅ The priority of round-robin mode is CH0 > CH1 > CH2 >

CH3 immediately after a reset.

When the round-robin mode is specified, cycle-steal mode

and burst mode should not be mixed among the bus modes

for multiple channels.

8.4.4 DMA Transfer Types

Address Modes

Figure 8.6 Example of

DMA Transfer Timing in

Dual Mode (Source:

Ordinary Memory,

Destination: Ordinary

Memory)

262

Figure amended

CKIO

A25 to A0

D31 to D0

WEn

DACKn

(Active-Low)

CSn

Transfer source

address

Transfer destination

address

Data read cycle

Data write cycle

(1st cycle)

(2nd cycle)

Bus Mode and channel

Priority Order

266

Description largely revised

8.5 Precautions

270

Newly added

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