AX88141

PRELIMINARY

ASIX ELECTRONICS CORPORATION

21

CONFIDENTIAL

4.2.8 Status Register (REG5)

1.

The status register contains all the status bits that the AX88141 reports to the host.

2.

Most of the fields in this register cause the host to be interrupted.

3.

REG5 bits are not cleared when read.

4.

Writing 1 to these bits clears them; writing 0 has no effect. Each field can be masked.

Field

R/W/C

Description

31:26

-

Reserved

25

24

23

Description

0

0

0

Parity error

0

0

1

Master abort

0

1

0

Target abort

0

1

1

Reserved

25:23

R

EB - Error Bits

(Not generate interrupt)

Indicates the type of error that

caused system error.

Valid only when fatal bus error

REG5<13> is set.

1

x

x

Reserved

22:20

-

Reserved.--Written as “0” for future compatibility concern.

19:17

-

Reserved.--Written as “0” for future compatibility concern.

NIS - Normal Interrupt Summary

Only the unmasked bits affect normal interrupt summary REG5<16> bit Normal interrupt summary bit. Its

value is the logical OR of :

CSR5<0>

transmit interrupt

CSR5<2>

transmit buffer unavailable

CSR5<6>

receive interrupt

CSR5<10>

Early transmit interrupt

16

R

CSR5<11>

General-purpose timer expired

AIS - Abnormal Interrupt Summary

Only unmasked bits affect only the abnormal interrupt summary REG5<15> bit.

Abnormal interrupt summary bits. Its value is the logical OR of :

CSR5<1>

transmit process stopped

CSR5<3>

transmit jabber time out

CSR5<5>

transmit under-flow

CSR5<7>

receive buffer unavailable

CSR5<8>

receive process stopped

CSR5<9>

receive watchdog time out

15

R

CSR5<13>

fatal bus error

13

R

FBE - Fatal Bus Error

Indicates that a system error occurred. If a system error occurs, all bus accesses are disabled

11

R/W/C

GTE - General Purpose Timer Expired

Indicates that the general-purpose timer (REG11) counter has expired. This timer is mainly used by the

software driver.

10

R/W/C

ETI - Early Transmit Interrupt

Indicates that the packet to be transmitted was fully transferred into the chip‘s internal transmit FIFOs.

Transmit interrupt (REG5<0>) automatically clears this bit.

9

R/W/C

RWT - Receive watchdog Time out

Indicates that the receive watchdog timer expired and another node is still active on the network. In case of

overflow, the long packets may not be received.

8

R/W/C

RPS - Receive Process Stopped

Asserts when the receive process enters stopped state.

7

R/W/C

RU - Receive Buffer Unavailable

Indicates the next descriptor in the receive list is owned by the host and cannot be acquired by the

AX88141.The reception process is suspended.

6

R/W/C

RI - Receive Interrupt

Indicates the completion of a frame reception. Specific frame status information has been posted in the

descriptor. The reception process remains in the running state.

5

R/W/C

UNF - Transmit Under-flow

Indicates that the transmit FIFO had an under-flow condition during the packet transmission. The transmit

process is placed in the suspended state and under-flow error TDES0<1> is set.

4

-

Reserved.--Written as “0” for future compatibility concern.