SC3200 datasheet(64/447 Pages) AMD

64 / 447 page

AMD Geode™ SC3200 Processor Data Book

Signal Definitions

Revision 5.1

FPCI_MON

Fast-PCI Monitoring. The strap on this ball

forces selection of Fast-PCI monitoring sig-

nals. For normal operation, strap this signal

low using a 1.5 K

Ω resistor. The value of this

strap can be read on the MCR[30].

PCICLK0

DID1

Device ID. Together, the straps on these sig-

nals define the system-level chip ID.

The value of DID1 can be read in the

MCR[29]. The value of DID0 can be read in

the MCR[31].

DID0 and DID1 must have a pull-up resistor

of 1.5 K

Ω.

GNT1#

DID0

GNT0#

POR#

J29

AH9

Power On Reset. POR# is the system reset

signal generated from the power supply to

indicate that the system should be reset.

---

X32I

C30

AJ2

I/O

Crystal Connections. Connected directly to

a 32.768 KHz crystal. This clock input is

required even if the internal RTC is not being

used. Some of the internal clocks are derived

from this clock. If an external clock is used, it

should be connected to X32I, using a voltage

level of 0 volts to VCORE +10% maximum.

X32O should remain unconnected.

---

X32O

D29

AJ3

---

X27I

A29

AG3

I/O

Crystal Connections. Connected directly to

a 27.000 MHz crystal. Some of the internal

clocks are derived from this clock. If an exter-

nal clock is used, it should be connected to

X27I, using a voltage level of 0 volts to VIO

and X27O should be remain unconnected.

---

X27O

D27

AH2

---

CLK27M

A23

AA4

27 MHz Output Clock. Output of crystal

oscillator.

IDE_DATA5

PCIRST#

PCI and System Reset. PCIRST# is the

reset signal for the PCI bus and system. It is

asserted for approximately 100 µs after

POR# is negated.

---

3.4.1

System Interface (Continued)

Signal Name

Ball No.

Type

Description

Mux

EBGA

TEPBGA

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