Advanced Clock Drivers Devices

2

Freescale Semiconductor

MPC9850

Figure 1. MPC9850 Logic Diagram

Table 1. Pin Configurations

Pin

I/O

Type

Function

Supply

Active/State

CLK

Input

LVCMOS

PLL Reference Clock Input (pull-down)

PCLK, PCLK

Input

LVPECL

PLL Reference Clock Input (PCLK - pull-down, PCLK - pull-up and

pull-down)

QA0, QA1, QA2, QA3 Output

LVCMOS

Bank A Outputs

QB0, QB1, QB2, QB3 Output

LVCMOS

Bank B Outputs

QC0, QC1, QC0,

QC1

Output

LVDS

Bank C Outputs

REF_OUT

Output

LVCMOS

Reference Output (25 MHz or 33 MHz)

XTAL_IN

Input

LVCMOS

Crystal Oscillator Input Pin

XTAL_OUT

Output

LVCMOS

Crystal Oscillator Output Pin

REF_CLK_SEL

Input

LVCMOS

Select between CLK and PCLK Input (pull-down)

High

REF_SEL

Input

LVCMOS

High

REF_33MHz

Input

LVCMOS

Selects 33 MHz Input (pull-down)

High

MR

Input

LVCMOS

Master Reset (pull-up)

Low

PLL_BYPASS

Input

LVCMOS

Select PLL or static test mode (pull-down)

High

1. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb)

Input

LVCMOS

Configures Bank A clock output frequency (pull-up)

High

2. PowerPC bit ordering (bit 0 = msb, bit 5 = lsb)

PowerPC bit ordering (bit 0 = msb, bit 1 = lsb)

Input

LVCMOS

Configures Bank B clock output frequency (pull-up)

High

RIO_C [0:1]

Input

LVCMOS

Configures Bank C clock output frequency (pull-down)

3.3 V Supply

Analog Supply

Supply for Output Bank A

Supply for Output Bank B

Supply for Output Bank C

GND

Ground

÷N

÷4, 8, 16, 40

QC0

PCLK

PCLK

CLK

REF_CLK_SEL

XTAL_IN

XTAL_OUT

REF_SEL

PLL_BYPASS

REF_33MHz

CLK_A[0:5]

CLK_B[0:5]

RIO_C[0:1]

MR

QC1

REF_OUT

QC1

QC0

QB3

QB2

QB1

QB0

QA3

QA2

QA1

QA0

÷N

PLL

2000 MHz

Ref

OSC

0

1

0

1

1

0