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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STW4810BHD 데이터시트(PDF) 13 Page - STMicroelectronics |
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STW4810BHD 데이터시트(HTML) 13 Page - STMicroelectronics |
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13 / 72 page  STw4810 4 Functional description Rev3 13/72 All regulators are started with PDN_regulators but can be switched off from the beginning or during application by software ( Table 26) . Registers reset In the event of a hardware reset coming from the modem, PON ball set to “0”, all registers are reset at initial value when PON ball goes back to “1” level. A software reset from multimedia processor of STw4810, through SW_RESETn ball set to “0”, reset all registers except power control register (at address 1E & 1F). Main clock oscillator control REQUEST_MC is an OR output gate between PWREN (coming from multimedia processor) and TCXO_EN (coming from modem supply), it is synchronized on 32 kHz, except during power-up where PWREN is masked and considered as high. REQUEST_MC enabled or disabled the master clock oscillator device. Figure 4. Switching POWER to sleep timing PDN_regulators VDDOK CLK32K PWREN Sleep regulators HPM SLEEP HPM MASTER_CLK Internal_OSC PDN_intOSC int_OSC _detect ~100µs REQUEST_MC |
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