LPC47N237-MD datasheet(17/138 Pages) SMSC

17 / 138 page

3.3v I/O Controller for Port Replicators and Docking Stations

SMSC DS – LPC47N237

Page 17

Revision 0.3 (10-26-04)

DATASHEET

PIN#

NAME

(NOTE 4.1)

DESCRIPTION

BUFFER

NAME

(NOTE 4.2)

PWR

WELL

(NOTE

4.3)

NOTES

LGP47

(SYSOPT)

LPC General Purpose I/O.

System Option. At trailing edge of

hardware reset this pin is latched to

determine the configuration base address:

0=Index Base I/O Address 0x2E; 1=Index

Base I/O Address 0x4E.

IO8

VCC

(Note 4.8)

SMBus GPIO BLOCK (40)

SCLK

SMBus Clock IOD

IS2OD12

VTR

SDAT

SMBus Data IOD

IS2OD12

VTR

nSMBINT

SMBus Interrupt Open-Drain Output

OD8

VTR

SMB_A0

LSB of SMBus Address sampled on VTR

POR. Connect to GND or pull-up to VTR.

VTR

15,49,

50,51,

52,54,

55,16

GP10-GP17

57-

59,

14,

40-43

GP20-GP27

11,

33-

38, 12

GP30-GP37

92,

94-

100

GP50-GP57

SMBus Controlled General Purpose I/O.

The GPIOs can be programmed as open-

drain output. These pins are either-edge

wakeup inputs and can be driven under

VTR power. The default is input on VTR

POR.

IO8

VTR

SCLK_1

SMBus Clock 1 IOD. This is an SMBus

Clock pin that can be isolated from the

SCLK pin (in conjunction with SDAT_1)

IS2OD12

VTR

SDAT_1

SMBus Data 1 IOD. This is an SMBus Data

pin that can be isolated from the SDAT pin

(in conjunction with SCLK_1)

IS2OD12

VTR

SCLK_2

SMBus Clock 2 IOD. This is an SMBus

Clock pin that can be isolated from the

SCLK pin (in conjunction with SDAT_2)

IS2OD12

VTR

SDAT_2

SMBus Data 2 IOD. This is an SMBus Data

pin that can be isolated from the SDAT pin

(in conjunction with SCLK_2)

IS2OD12

VTR

LPC47N237-MD 데이터시트(PDF) 17 Page - SMSC Corporation

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