FXLS8974CF datasheet(55/96 Pages) NXP

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NXP Semiconductors

FXLS8974CF

3-Axis Low-g Accelerometer

WAKE mode ODR (Hz)

WAKE mode

ODR Period (ms)

ASLP_COUNT Period (ms)

Max Inactivity Times

400

2.5

10.24

200

20.48

100

40.96

81.92

163.84

12.5

327.68

6.25

160

655.36

3.125

320

1310.72

1.563

640

2621.44

0.781

1280

5242.54

Table 69. ASLP_COUNT timer period...continued

Interrupt Event

Source

Event flag can clear auto-sleep timer?

Event flag can transition the device from

SLEEP to WAKE mode?

SRC_DRDY

SRC_OVF

SRC_BUF

Yes[1]

SRC_SDCD_OT

Yes

SRC_SDCD_WT

Yes

SRC_ORIENT

Yes

SRC_ASLP

No[2]

SRC_BOOT

Table 70. Auto-WAKE/SLEEP Interrupt Event Sources

[1]

When BUF_CONFIG2[WAKE_SRC_BUF] = 1, clearing the SRC_BUF event flag resets the auto-sleep timer and prevent FXLS8974CF from entering

SLEEP mode. When BUF_CONFIG2[WAKE_SRC_BUF] = 0 (default), FXLS8974CF enters SLEEP mode regardless of the state of the BUF_WMRK or

BUF_OVF event flags.

[2]

If the BUF_GATE bit is set to logic '1', it prevents the output buffer from accepting new data after a WAKE-to-SLEEP or SLEEP-to-WAKE operating mode

transition until the host first empties the buffer contents. The BUF_GATE bit is useful for preventing acceleration data from different WAKE and SLEEP

mode ODRs from being mixed within the buffer.

15.21 INT_EN register (address 20h)

This register is used to enable and disable the various interrupt event generators

embedded within the device.

Note:

• When BT_MODE = VDD, the INT1/MOT_DET pin signals any mapped (and enabled)

interrupts with a TPULSE-MOT ms active low pulse (open-drain output with external pull-

up).

• Any enabled interrupt is signaled with a TPULSE-MOT ms pulse at the ODR rate until the

respective interrupt source flag is cleared.

FXLS8974CF

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 27 April 2021

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