MPF7100BVMA3ES datasheet(70/125 Pages) NXP

70 / 125 page

NXP Semiconductors

PF7100

7-channel power management integrated circuit for high performance applications

PF7100

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Product data sheet

Rev. 4 — 9 March 2021

70 / 125

Table 54. SW5 current limit selection

SW5ILIM[1:0]

Typical current limit

2.1 A

2.6 A

3.0 A

4.5 A

The current limit specification is given with respect to the inductor peak current. To

calculate the DC current at which the buck regulator enters into current limitation, it is

necessary to calculate the inductor ripple current. An ideal approximation is enough to

obtain the ripple current as follows:

ΔiL = VOUT × (1 − VOUT/VIN)/(L × FSW)

L is the inductance value and FSW is the selected switching frequency.

The DC current limit is then calculated by:

DC ILIM = ILIM − (ΔiL / 2)

In order to account for component tolerances, use the minimum inductor value per the

inductor specification.

Regulator SW5 uses 3 bits (SW5PHASE[2:0]) to control the phase shift of the switching

frequency. The SW5 switching phase is loaded from the OTP_SW5PHASE[2:0] registers

at power up, it can be modified during the system-on states.

Table 55. SW5 phase configuration

SW5_PHASE[2:0]

Phase shift (degrees)

000

001

010

135

011

180

100

225

101

270

110

315

111

SW5 buck regulator provides two OTP bits to configure the value of the inductor used in

the power stage. The OTP_SW5_LSELECT[1:0] allow to choose the inductor as shown

in the following table.

Table 56. SW5 inductor selection bits

OTP_SW5_LSELECT[1:0]

Inductor value

1.0 µH

0.47 µH

1.5 µH

Reserved

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