2

ICS95V842

0830A—09/10/04

Pin Descriptions

PIN #

PIN NAME

PIN TYPE

DESCRIPTION

1

VDD2.5

PWR

Power supply, nominal 2.5V

2

DDRT0

OUT

"True" Clock of differential pair output.

3

DDRC0

OUT

"Complementary" Clock of differential pair output.

4

GND

PWR

Ground pin.

5

CLK_INT

IN

"True" reference clock input.

6

CLK_INC

IN

"Complementary" reference clock input.

7

AVDD

PWR

3.3V Analog Power pin for Core PLL

8AGND

PWR

Analog Ground pin for Core PLL

9

FB_OUTC

OUT

Complement single-ended feedback output, dedicated external

feedback. It switches at the same frequency as other DDR outputs,

This output must be connect to FB_INC.

10

FB_OUTT

OUT

True single-ended feedback output, dedicated external feedback. It

switches at the same frequency as other DDR outputs, This output

must be connect to FB_INT.

11

FB_INT

IN

True single-ended feedback input, provides feedback signal to internal

PLL for synchronization with CLK_INT to eliminate phase error.

12

FB_INC

IN

Complement single-ended feedback input, provides feedback signal to

internal PLL for synchronization with CLK_INT to eliminate phase

error.

13

VDD2.5

PWR

Power supply, nominal 2.5V

14

DDRT1

OUT

"True" Clock of differential pair output.

15

DDRC1

OUT

"Complementary" Clock of differential pair output.

16

GND

PWR

Ground pin.