Figure 4-5. PD69220 Top-Layer Solder Paste and Vias PCB Layout for Thermal Pad Array

Note: The contract manufacturer has latitude to modify the solder paste stencil for manufacturability reasons. The

solder paste stencil covers 65% to 80% of the thermal pad and must not allow solder to be applied to the thermal vias

under the QFN package using any method they deem appropriate. Any design should be subject to system validation

and qualification prior to commitment to mass production of field deployment. Use a 5 mil stencil.

The PD69220 may be used on a PCB that was designed for the PD69200, that is the top layer copper for the two

devices is identical. However, the recommended solder paste stencil for the PD69220 is different than the

recommended stencil for PD69200. The recommended solder paste stencil for the PD69200 is identical to the

PD69210 as shown in figure PD69210 Top-Layer Solder Paste and Vias PCB Layout for Thermal Pad Array. For

more information, see the PD69200 Datasheet.

4.5

Recommended Solder Reflow Information

RoHS 6/6

Pb-free 100% Matte Tin Finish

Package Peak Temperature for Solder Reflow (40 s maximum exposure)—260 °C (0 °C, –5 °C)

Table 4-4. Classification Reflow Profiles

Profile Feature

Sn-Pb Eutectic Assembly

Pb-Free Assembly

3 °C/second max

3 °C/second max

Preheat

100 °C

150 °C

150 °C

200 °C

60 s to 120 s

60 s to 180 s

Time Maintained

183 °C

217 °C

60 s to 150 s

60 s to 150 s

Peak classification temperature (TP)

210 °C to 235 °C

240 °C to 255 °C

PD69210/PD69220

Package Information

Datasheet

DS00003424A-page 15