Advanced Clock Drivers Devices

8

Freescale Semiconductor

MPC9239

Figure 4. Serial Interface Timing Diagram

Power Supply Filtering

The MPC9239 is a mixed analog/digital product. Its analog

circuitry is naturally susceptible to random noise, especially if

this noise is seen on the power supply pins. Random noise

MPC9239 provides separate power supplies for the digital

The purpose of this design technique is to try and isolate the

high switching noise digital outputs from the relatively

sensitive internal analog phase-locked loop. In a controlled

environment such as an evaluation board, this level of

isolation is sufficient. However, in a digital system

environment where it is more difficult to minimize noise on the

power supplies a second level of isolation may be required.

The simplest form of isolation is a power supply filter on the

power supply filter scheme. The MPC9239 is most

susceptible to noise with spectral content in the 1 kHz to

1 MHz range. Therefore, the filter should be designed to

target this range. The key parameter that needs to be met in

the final filter design is the DC voltage drop that will be seen

20 mA, assuming that a minimum of 2.835 V must be

Figure 5 must have a resistance of 10-15

Ω to meet the

voltage drop criteria. The RC filter pictured will provide a

broadband filter with approximately 100:1 attenuation for

noise whose spectral content is above 20 kHz. As the noise

frequency crosses the series resonant point of an individual

capacitor its overall impedance begins to look inductive and

thus increases with increasing frequency. The parallel

capacitor combination shown ensures that a low impedance

path to ground exists for frequencies well above the

bandwidth of the PLL. Generally, the resistor/capacitor filter

will be cheaper, easier to implement and provide an adequate

level of supply filtering. A higher level of attenuation can be

achieved by replacing the resistor with an appropriate valued

inductor. A 1000

µH choke will show a significant impedance

at 10 kHz frequencies and above. Because of the current

pin, a low DC resistance inductor is required (less than 15

Ω).

Table 10. Test and Debug Configuration for TEST

T[2:0]

TEST Output

T2

T1

T0

0

0

0

1. Clocked out at the rate of S_CLOCK.

0

0

1

Logic 1

0

1

0

0

1

1

M-Counter out

1

0

0

1

0

1

Logic 0

1

1

0

M-Counter out in PLL-bypass mode

1

1

1

1. T[2:0] = 110. AC specifications do not apply in PLL bypass

mode.

Output

Configuration

S_CLOCK

÷ N

TEST

2. Clocked out at the rate of S_CLOCK

÷ (2 ⋅ N)

S_CLOCK

S_DATA

S_LOAD

M[6:0]

N[1:0]

P_LOAD

T2

T1

T0

N1

N0

M6

M5

M4

M3

M2

M1

M0

M, N

First

Bit

Last

Bit

MPC9239