PLL620-00

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991

www.phaselink.com Rev 09/03/04 Page 1

FEATURES

Overtone Crystal input.

• Output range: 100 – 200MHz (no multiplication),

200 – 400MHz (2x multiplier) or 400 – 700MHz

(4x multiplier).

• Available outputs: PECL, LVDS, or CMOS (High

Drive (30mA) or Standard Drive (10mA) output).

• Supports 3.3V-Power Supply.

• Available in die form.

• Thickness 10 mil.

DESCRIPTION

The PLL620-00 is an XO IC specifically designed to

work with high frequency fundamental and third

overtone crystals. Its design was optimized to

tolerate higher limits of interelectrode capacitance

and bonding capacitance to improve yield. It

achieves very low current into the crystal resulting in

better overall stability. It is ideal for XO applications

requiring LVDS or PECL output levels at high

frequencies.

DIE SPECIFICATIONS

Name

Value

Size

62 x 65 mil

Reverse side

GND

Pad dimensions

80 micron x 80 micron

Thickness

10 mil

BLOCK DIAGRAM

DIE CONFIGURATION

OUTPUT SELECTION AND ENABLE

OUTSEL1

(Pad #18)

OUTSEL0

(Pad #25)

Selected Output

0

0

High Drive CMOS

0

1

Standard CMOS

1

0

LVDS

1

1

PECL (default)

OE_SELECT

(Pad #9)

OE_CTRL

(Pad #30)

State

0

Tri-state

0

1 (Default)

Output enabled

0 (Default)

Output enabled

1 (Default)

1

Tri-state

Pad #9:

Bond to GND to set to “0”, bond to VDD to set to “1”

Pad #30: Logical states defined by PECL levels if OE_SELECT (pad

#9) is “1”

Logical states defined by CMOS levels if OE_SELECT is

“0”

X+

X-

OE

Q

PLL620-00

Vin

Q

PLL by-pass

SEL

PLL

(Phase

Locked

Loop)

Oscillator

Amplifier

18

19

20

21

23

25

7

13

10

26

29

31

Y

X

(0,0)

(1550,1475)

65 mil

24

22

17

16

15

14

12

11

9

8

6

1

2

3

4

5

27

28

30

OE_SEL^

PECL

LVDS

VDDBUF

VDDBUF

PECLB

LVDSB

CMOS

GNDBUF

XIN

XOUT

NC

OE

CTRL

SEL2^

SEL3^

Die ID:

A1010-10A

C502A