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PL611-30XXXSC-R 데이터시트(PDF) 3 Page - PhaseLink Corporation

부품명 PL611-30XXXSC-R
상세설명  Programmable Quick Turn Clock
PDF  7 Pages
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제조업체  PLL [PhaseLink Corporation]
홈페이지  http://www.phaselink.com
Logo PLL - PhaseLink Corporation

PL611-30XXXSC-R 데이터시트(HTML) 3 Page - PhaseLink Corporation

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Preliminary
PL611-30
Programmable Quick Turn ClockTM
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com Rev 03/03/05 Page 3
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage Range
VDD
-0.5
4.6
V
Input Voltage Range
VI
-0.5
VDD
+0.5
V
Output Voltage Range
VO
-0.5
VDD
+0.5
V
Data Retention @ 85
º C
10
Years
Soldering Temperature
240
°C
Storage Temperature
TS
-65
150
°C
Ambient Operating Temperature*
-40
+85
°C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied.
AC SPECIFICATIONS
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Fundamental Crystal
10
30
MHz
Crystal Input Frequency
3rd Overtone Crystal
75
MHz
Settling Time
At power-up (after VDD increases over
1.62V)
10
ms
VDD Sensitivity
Frequency vs. VDD+/-10%
-2
2
ppm
15pF Load, 10/90%VDD, Standard drive
2.5
3.5
ns
Output Rise Time
15pF Load, 10/90%VDD, High drive
1.0
1.5
ns
15pF Load, 90/10%VDD, Standard drive
2.5
3.5
ns
Output Fall Time
15pF Load, 90/10%VDD, High drive
1.0
1.5
ns
Duty Cycle
At VDD/2
45
50
55
%
Max. output skew between
same frequency clocks
Equal loading (15 pF). Equal frequency
& drive strength
500
ps
Period Jitter, peak-to-peak*
(measured from 10,000
samples)
With capacitive decoupling between VDD
and GND. Operating only one output.
40
ps
* Note: Jitter performance depends on the programming parameters.



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