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AT25QL128A 데이터시트(PDF) 21 Page - Dialog Semiconductor

부품명 AT25QL128A
상세설명  1.7 V Minimum, 128-Mbit SPI Serial Flash Memory with Dual I/O, Quad I/O, and QPI Support
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AT25QL128A
DS-AT25QL128A–129E–01-2021
8.2
Write Enable (06h)
The Write Enable instruction is for setting the Write Enable Latch (WEL) bit in the Status Register. The WEL bit
must be set before every Program, Erase, and Write Status Register instruction. To enter the Write Enable
instruction, CS goes low before the instruction 06h into Data Input (SI) pin on the rising edge of SCK; then CS
goes high.
Figure 8-1. Write Enable Instruction for SPI Mode (left) and QPI Mode (right)
Reset
99h
Disable QPI
FFh
Burst Read with
Wrap
up to 80
MHz
0Ch
A23:A16
A15:A8
A7:A0
Dummy
Dummy
(D7:D0)
up to 104
MHz
A23:A16
A15:A8
A7:A0
Dummy
Dummy
Dummy
(D7:D0)
up to 133
MHz
A23:A16
A15:A8
A7:A0
Dummy
Dummy
Dummy
Dummy
(D7:D0)
Set Read Parameter
C0h
P7:P0
Quad Page Program
33h
A23:A16
A15:A8
A7:A0
(D7:D0)
1.
Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “()” indicate data being read from the device on the IO pin.
2.
SR = Status Register. The Status Register contents and Device ID repeat continuously until CS terminates the instruction.
3.
At least one byte of data input is required for Page Program, Quad Page Program and Program Security Register, up to 256 bytes of data input. If more than 256 bytes
of data are sent to the device, the addressing wraps to the beginning of the page and overwrites previously sent data.
4.
See Manufacturer and Device Identification table for Device ID information.
5.
SC = Security Register.
Table 8-5. Instruction Set Table 4 (QPI Instructions) (Continued)
Instruction Byte (1)
0
1
2
3
4
5
6
7
8
Clock Number
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
16, 17
03
5
246
7
1
Mode 3
Mode 0
Mode 3
Mode 0
High Impedace
DO(IO
DI(IO
IO
IO
IO
IO
SCK
SCK
CS
Instruction
0
1
Mode 3
Mode 0
Mode 3
Mode 0
CS



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