PRELIMINARY

PLL650-10

Network LAN Clock for Gigabit Ethernet

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 12/10/02 Page 1

FEATURES

• Full CMOS output swing with 40-mA output drive

capability. 25-mA output drive at TTL level.

• Advanced, low power, sub-micron CMOS processes.

• 25MHz fundamental crystal or clock input.

• Two outputs fixed at 125MHz..

• Zero PPM synthesis error in all clocks.

• Ideal for Network switches.

• 3.3V operation.

•

DESCRIPTIONS

The PLL 650-10 is a low cost, low jitter, and high

performance clock synthesizer. With PhaseLink’s

proprietary analog Phase Locked Loop techniques, the chip

accepts 25MHz crystal, and produces multiple output

clocks for networking chips, and ASICs.

PIN CONFIGURATION

BLOCK DIAGRAM

XTAL

OS C

125MHz

XIN

XO UT

125MHz

Control

Logic

1

2

3

4

5

6

7

8

VDD

GND

VDD

125MHz

XIN

XOUT

GND

125MHz