ADPA7005CHIP datasheet(14/23 Pages) AD

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ADPA7005CHIP

Data Sheet

Rev. 0 | Page 14 of 23

THEORY OF OPERATION

The architecture of the ADPA7005CHIP, a medium power

amplifier, is shown in Figure 50. The ADPA7005CHIP uses two

cascaded, three stage amplifiers operating in quadrature

between six 90° hybrids.

The input signal is divided evenly into two, and then each signal

is divided into two again. Each of these new paths are amplified

through three independent gain stages. The amplified signals

are then combined at the output. This balanced amplifier

approach forms an amplifier with a combined gain of 15 dB and

a PSAT value of 32 dBm.

A portion of the RF output signal is directionally coupled to a

diode for detection of the RF output power. When the diode is

dc biased, the diode rectifies the RF power and makes the RF

power available for measurement as a dc voltage at VDET. To

allow temperature compensation of VDET, an identical and

symmetrically located circuit, minus the coupled RF power, is

available via VREF. Taking the difference of VREF − VDET

provides a temperature compensated signal that is proportional

to the RF output (see Figure 50).

The 90° hybrids ensure that the input and output return losses

are greater than 15 dB. See the application circuits shown in

Figure 63 and Figure 64 for further details on biasing the

various blocks.

Figure 50. ADPA7005CHIP Architecture

DIRECTIONAL

COUPLER

90° COUPLER

VREF VDET

RFOUT

RFIN

90° COUPLER

THREE STAGE BALANCED AMPLIFIER

90° COUPLER

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