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PLL602-89DSC-R 데이터시트(PDF) 1 Page - PhaseLink Corporation |
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PLL602-89DSC-R 데이터시트(HTML) 1 Page - PhaseLink Corporation |
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1 / 5 page ![]() PLL602-89D 12-27 MHz XO IC with 2 Pairs of LVDS Outputs 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 1 FEATURES • Low jitter XO for the 12MHz to 27MHz range. • Integrated crystal load capacitor: no external load capacitor required. • 2 pairs of LVDS outputs. • 12-27 MHz fundamental crystal input. • Low jitter (RMS): 2.5 ps period jitter (1 sigma). • 2.5V to 3.3V operation. • Available in 8-Pin SOIC package. PIN CONFIGURATION (Top View) DESCRIPTION The PLL602-89D is a high performance multiple output XO IC chip. It provides 2 pairs of LVDS outputs. The chip combines a crystal oscillator (XO) with a multiple-output buffer. It accepts a low cost fundamental parallel resonant mode crystal from 12MHz to 27MHz, which is reproduced at the outputs. The very low jitter (2.5 ps RMS period jitter) makes this chip ideal for data and telecommunication applications. BLOCK DIAGRAM 1 2 3 45 6 7 8 VDD XIN XOUT GND LVDS1_CLK LVDS2_CLK LVDS2BAR_CLK LVDS1BAR_CLK XOUT LVDS2_CLK XIN Oscillator Amplifier LVDS2BAR_CLK LVDS1_CLK LVDS1BAR_CLK (8 pin SOIC) |
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