| 전자부품 데이터시트 검색엔진 |
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PLL620-3XOC 데이터시트(PDF) 3 Page - PhaseLink Corporation |
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PLL620-3XOC 데이터시트(HTML) 3 Page - PhaseLink Corporation |
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3 / 6 page ![]() PLL620-38/-39 PECL and LVDS Low Phase Noise XO (for 32.5-130MHz Output) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/15/05 Page 3 3. General Electrical Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Supply Current (Loaded Outputs) IDD PECL/LVDS 100/80 mA Operating Voltage VDD 2.97 3.63 V Output Clock Duty Cycle @ 1.25V (LVDS) @ VDD – 1.3V (PECL) 45 45 50 50 55 55 % Short Circuit Current ±50 mA 4. Jitter Specifications PARAMETERS CONDITIONS MIN. TYP. MAX. UNITS Period jitter RMS 77.76MHz 2.5 ps Period jitter peak-to-peak 77.76MHz 18.5 ps Integrated jitter RMS Integrated 12kHz to 20MHz at 77.76MHz 0.5 ps 5. Phase Noise Specifications PARAMETERS FREQUENCY @10Hz @100Hz @1kHz @10kHz @100kHz UNITS Phase Noise relative to carrier 77.76MHz -75 -95 -125 -145 -155 dBc/Hz |
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