AT45DB021E-DWF datasheet(35/74 Pages) DIALOG

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AT45DB021E

DS-AT45DB021E—8789J—03/2021

Deep Power-Down

During normal operation, the device is placed in the standby mode to consume less power as long as the CS pin

remains deasserted and no internal operation is in progress. The Deep Power-Down command offers the ability to

place the device into an even lower power consumption state called the Deep Power-Down mode.

When the device is in the Deep Power-Down mode, all commands, including the Status Register Read command,

are ignored with the exception of the Resume from Deep Power-Down command. Since all commands are ignored,

the mode can be used as an extra protection mechanism against program and erase operations.

Entering the Deep Power-Down mode is done by asserting the CS pin, clocking in the opcode B9h, and then

deasserting the CS pin. Any additional data clocked into the device after the opcode are ignored. When the CS pin

is deasserted, the device enters the Deep Power-Down mode within the maximum time of tEDPD.

The complete opcode must be clocked in before the CS pin is deasserted; otherwise, the device aborts the

operation and returns to the standby mode once the CS pin is deasserted. Also, the device defaults to the standby

mode after a power cycle.

The Deep Power-Down command is ignored if an internally self-timed operation such as a program or erase cycle

is in progress. The Deep Power-Down command must be reissued after the internally self-timed operation has

been completed in order for the device to enter the Deep Power-Down mode.

Figure 11-1. Deep Power-Down Timing

SCK

MSB

10111001

OPCODE

HIGH-IMPEDANCE

Standby Mode Current

Active Current

Deep Power-Down Mode Current

tEDPD

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