PLL650-01

Low EMI Network LAN Clock

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 2

PIN DESCRIPTIONS

Name

Number

Type

Description

CLKA1

17

O

Clock A Output. Frequency Select pin selectable via (FS0 ~ FS4).

CLKA2

13

O

Clock A Output. Frequency Select pin selectable via (FS0 ~ FS4).

CLKB1

10

O

Clock B Output. Frequency Select pin selectable via (FS0 ~ FS4).

CLKB2

9

O

Clock B Output. Frequency Select pin selectable via (FS0 ~ FS4).

CLKC1

7

O

Clock C Output. Selectable from jumper CS0 and table CS1 output.

CLKC2

8

O

Clock C Output. Selectable from jumper CS0 and table CS1 output.

XIN

3

I

Crystal input to be connected to a fundamental crystal or clock input.

XOUT

2

O

Crystal Connection.

FS2

19

I

Frequency Select 2. Select outputs per table on page 3.

FS3

20

I

Frequency Select 3. Select outputs per table on page 3.

CS0

11

I

Clock C select pin. Select outputs for CLKC1, CLKC2.

FS0

1

I

Frequency Select 0. Select outputs per table on page 3.

FS1

5

I

Frequency Select 1. Select outputs per table on page 3.

FS4

12

I

Frequency Select 4. Select outputs per table on page 3.

OE

15

I

Output Enable. When low, Tri-states all outputs.

REF/CS1

18

B

Buffered Reference Clock Outputs. Same frequency as crystal or clock input.

This pin latches CS1 value at power up and select outputs for CLKC1,

CLKC2 (See table on page 3). Has internal pull-up resistor.

VDD

4,16

P

3.3V power supply.

GND

6,14

P

Ground.