PCF8545ATT datasheet(9/51 Pages) NXP

9 / 51 page

NXP Semiconductors

PCF8553

40 × 4 LCD segment driver

tw(rst) = 10 µs

minimum

tw(rst) = 10 µs

minimum

VDD(min)

VDD

RST

Valid reset pulse

during power-up

Valid reset pulse

after power-up

aaa-017468

Figure 4. Reset pulse timing

Alternatively a software reset can be applied (see Section 7.3.4).

Following a reset, the register 00h has to be rewritten with 0h by the next command byte

or the address pointer AP[4:0] has to be set to the required address after a new START

procedure.

7.3.1 Power-down mode

After a reset, the PCF8553 remains in power-down mode. In power-down mode the

oscillator is switched off and there is no output on pin CLK. The register settings remain

unchanged and the bus remains active. To enable the PCF8553, bit DE (command

Display_ctrl_1, see Table 6) must be set to logic 1.

7.3.2 Power-On Reset (POR)

If pin PORE is connected to VDD, the PCF8553 comprises an internal POR, which puts

the device into the following starting conditions:

• All backplane and segment outputs are set to VSS

• The selected drive mode is: 1:4 multiplex with 1⁄3 bias

• Blinking is switched off

• The address pointer is cleared (set to logic 0)

• The display and the internal oscillator are disabled

• The display registers are set to logic 0

• The bus interface is initialized

Remark: The internal POR can be disabled by connecting pin PORE to VSS. In this

case, the internal registers are not defined and require a hardware reset according to

Section 7.3.3 or a software reset, see Section 7.3.4.

7.3.3 Hardware reset: RST pin

At power-on the PCF8553 can be reset to the following starting conditions by pulling pin

RST low:

• All backplane and segment outputs are set to VSS

• The selected drive mode is: 1:4 multiplex with 1⁄3 bias

• Blinking is switched off

PCF8553

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 20 April 2021

9 / 51

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