| 전자부품 데이터시트 검색엔진 |
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P701-17SC 데이터시트(PDF) 4 Page - PhaseLink Corporation |
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P701-17SC 데이터시트(HTML) 4 Page - PhaseLink Corporation |
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4 / 5 page ![]() PLL701-17 Low EMI Spread Spectrum Multiplier Clock 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/17/06 Page 4 FUNCTIONAL DESCRIPTION Selectable spread spectrum and modulation frequency and magnitude The PLL701-17 provides selectable spread spectrum modulation frequency, as well as selectable modulation magnitude. Selection is made by connecting pins 2 (S2), 3 (S1), 4 (S0), and 7 (S3) to a logical “zero” or “one”, according to the output clock selection table on (page 1). Default values for S(0:3) through internal pull-up and pull-down resistor Selection pins 4 and 7 (S0 and S3) have an internal pull-down resistor of 30k Ω while pins 2 and 3 (S1 and S2) have an internal pull-up resistor of 30k Ω. This internal pull-down (or pull-up) resistor will pull the input value to a logical “zero” (or “one” respectively) by default, i.e. when no connection is made between the pin and VDD (GND respectively). In order to override the internal pull-down (pull-up), the pin has to be connected to VDD (GND respectively). |
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