| 전자부품 데이터시트 검색엔진 |
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PLL502-10 데이터시트(PDF) 2 Page - PhaseLink Corporation |
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PLL502-10 데이터시트(HTML) 2 Page - PhaseLink Corporation |
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2 / 8 page ![]() Preliminary PLL502-10 750kHz – 400MHz Low Phase Noise VCXO (for 12 – 25MHz Crystals) 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 11/06/02 Page 2 FREQUENCY SELECTION TABLE Pad #28 SEL3 Pad #29 SEL2 Pad #19 SEL1 Pad #20 SEL0 Selected Multiplier 0 0 0 0 Reserved 0 0 0 1 Reserved 0 0 1 0 Reserved 0 0 1 1 Reserved 0 1 0 0 Reserved 0 1 0 1 Reserved 0 1 1 0 Fin / 8 0 1 1 1 Fin x 2 1 0 0 0 Reserved 1 0 0 1 Fin / 2 1 0 1 0 Fin / 16 1 0 1 1 Fin x 4 1 1 0 0 Fin / 4 1 1 0 1 Fin x 8 1 1 1 0 Fin x 16 1 1 1 1 No multiplication All pads have internal pull-ups (default value is 1). Bond to GND to set to 0. |
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