ICS525-07/08

MDS 525-07/08 A

1

Revision 101105

Integrated Circuit Systems, Inc.

LVCMOS User Configurable Clock

PRELIMINARY INFORMATION

Description

The ICS525-07/08 are the most flexible way to

generate a high-quality clock output from an

inexpensive crystal or clock input at low supply

voltages. The user can configure the device to produce

nearly any output frequency from any input frequency

by grounding or floating the select pins or by driving or

hard wiring the select pins high or low. Neither

microcontroller, software, nor device programmer are

needed to set the frequency. Using Phase-Locked

Loop (PLL) techniques, the device accepts a standard

fundamental mode, inexpensive crystal to produce

output clocks up to 250 MHz. It can also produce a

highly accurate output clock from a given input clock,

keeping them frequency locked.

For similar capability with a serial interface, use the

ICS307.

This product is intended for clock generation. It has low

output jitter (variation in the output period), but input to

output skew is not defined nor guaranteed.

Features

internal dividers

ranges

Block Diagram

VDD

GND

2

2

CLK

REF

Reference

Divider

Phase Comparator,

Charge Pump, and

Loop Filter

VCO

VCO

Divider

Output

Divider

R Configuration Pins

V Configuration Pins

S Configuration Pins

X1/ICLK

X2

Crystal or clock

input

Optional crystal capacitors

Crystal

Oscillator

PD

VDD

GND

2

2

CLK

REF

Reference

Divider

Phase Comparator,

Charge Pump, and

Loop Filter

VCO

VCO

Divider

Output

Divider

R Configuration Pins

V Configuration Pins

S Configuration Pins

X1/ICLK

X2

Crystal or clock

input

Optional crystal capacitors

Crystal

Oscillator

PD