Clock Divider

MDS 544M-01 A

3

Revision 041505

Integrated Circuit Systems, Inc.

ICS544-01

PRELIM INAR Y INFO RMA T ION

VDD pin as possible. No vias should be used between

decoupling capacitor and VDD pin. The PCB trace to

VDD pin should be kept as short as possible, as should

the PCB trace to the ground via. Distance of the ferrite

bead and bulk decoupling from the device is less

critical.

2) To minimize EMI, the 33

Ω series termination resistor

(if needed) should be placed close to the clock output.

3) An optimum layout is one with all components on the

same side of the board, minimizing vias through other

signal layers (the ferrite bead and bulk decoupling

capacitor can be mounted on the back). Other signal

traces should be routed away from the ICS544-01. This

includes signal traces just underneath the device, or on

layers adjacent to the ground plane layer used by the

device.

Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the ICS544-01. These ratings,

which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of

the device at these or any other conditions above those indicated in the operational sections of the

specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can

affect product reliability. Electrical parameters are guaranteed only over the recommended operating

temperature range.

Recommended Operation Conditions

Item

Rating

Supply Voltage, VDD

7 V

All Inputs and Outputs

-0.5 V to VDD+0.5 V

Ambient Operating Temperature

0 to +70

°C

Storage Temperature

-65 to +150

°C

Junction Temperature

125

°C

Soldering Temperature

260

°C

Parameter

Min.

Typ.

Max.

Units

Ambient Operating Temperature

-40

+85

°C

Power Supply Voltage (measured in respect to GND)

2.25

3.6

V