ADUCM3027BCPZ-R7 datasheet(12/39 Pages) AD

12 / 39 page

ADuCM3027/ADuCM3029

Data Sheet

Rev. B | Page 12 of 39

SPI Timing

Table 13.

Parameter1

Symbol

Min

Typ

Max

Unit

SPI MASTER MODE TIMING

Timing Requirements

Chip Select (CS) to Serial Clock (SCLK) Edge

tCS

(0.5 × tPCLK) − 3

SCLK Low Pulse Width

tSL

tPCLK − 3.5

SCLK High Pulse Width

tSH

tPCLK − 3.5

Data Input Setup Time Before SCLK Edge

tDSU

Data Input Hold Time After SCLK Edge

tDHD

Switching Characteristics

Data Output Valid After SCLK Edge

tDAV

Data Output Setup Before SCLK Edge

tDOSU

tPCLK − 2.2

CS High After SCLK Edge

tSFS

(0.5 × tPCLK) − 3

SPI SLAVE MODE TIMING

Timing Requirements

CS to SCLK Edge

tCS

38.5

SCLK Low Pulse Width

tSL

38.5

SCLK High Pulse Width

tSH

38.5

Data Input Setup Time Before SCLK Edge

tDSU

Data Input Hold Time After SCLK Edge

tDHD

Switching Characteristics

Data Output Valid After SCLK Edge

tDAV

Data Output Valid After CS Edge

tDOCS

CS High After SCLK Edge

tSFS

38.5

1 These specifications are characterized with respect to double drive strength.

MOSI

MSB

MSB IN

BIT 6 TO BIT 1

LSB

LSB IN

BIT 6 TO BIT 1

MISO

SCLK

(POLARITY = 0)

SCLK

(POLARITY = 1)

tCS

tSFS

tSH

tDAV

tDSU

tDHD

tSL

Figure 8. SPI Master Mode Timing (Phase Mode = 1)

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