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2021 Microchip Technology Inc.

DS20006510B-page 7

VC-830

3.0

APPLICATION DIAGRAMS

3.1

LVPECL Application Diagrams

The VC-830 incorporates a standard PECL output scheme, which are unterminated FET drains. There are numerous

application notes on terminating and interfacing PECL logic and the two most common methods are a single resistor to

ground (Figure 3-1) and a pull-up/pull-down scheme as shown in Figure 3-2. AC-coupling capacitors are optional,

depending on the application and the input logic requirements of the next stage.

One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused

output should not be left unterminated because if one of the two outputs is left open, it will result in excessive jitter on

both. PCB layout must take this and 50Ω impedance matching into account. Load matching and power supply noise are

the main contributors to jitter related problems.

FIGURE 3-1:

Pull-Down Resistor

Termination Scheme.

Figure 3-1 shows one option to terminate LVPECL

outputs and is optimized to reduce common mode

noise. R1 is 50Ω for 3.3V supply voltage and 18Ω for

2.5V.

FIGURE 3-2:

Pull-Up/Pull-Down

Termination.

Resistor values shown are typical for 3.3V operation.

For 2.5V operation, the resistor to ground is 62Ω and

the resistor to supply is 250Ω.