85314AGI-11

www.icst.com/products/hiperclocks.html

REV. C MAY 24, 2005

10

Integrated

Circuit

Systems, Inc.

ICS85314I-11

The clock layout topology shown below is a typical termi-

nation for LVPECL outputs. The two different layouts men-

tioned are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, ter-

minating resistors (DC current path to ground) or current

sources must be used for functionality. These outputs are

V

50

Ω

50

Ω

RTT

Z

Z

FOUT

FIN

RTT =

Z

o

1

((V

3.3V

125

Ω

125

Ω

84

Ω

84

Ω

Z

Z

FOUT

FIN

designed to drive 50

Ω transmission lines. Matched imped-

ance techniques should be used to maximize operating

frequency and minimize signal distortion. Figures 4A and

4B show two different layouts which are recommended only

as guidelines. Other suitable clock layouts may exist and it

would be recommended that the board designers simulate

to guarantee compatibility across all printed circuit and clock

component process variations.