843002AGI-01

www.icst.com/products/hiperclocks.html

REV. A JANUARY 6, 2006

10

Integrated

Circuit

Systems, Inc.

ICS843002I-01

Figure 5A shows a schematic example of the ICS843002I-01.

An example of LVEPCL termination is shown in this schematic.

Additional LVPECL termination approaches are shown in the

LVPECL Termination Application Note. In this example, an 18 pF

parallel resonant 26.5625MHz crystal is used. The C1=27pF

and C2=33pF are recommended for frequency accuracy. For

different board layout, the C1 and C2 may be slightly adjusted

for optimizing frequency accuracy.

Figure 5B shows an example of ICS843002I-01 P.C. board lay-

out. The crystal X1 footprint shown in this example allows in-

stallation of either surface mount HC49S or through-hole HC49

package. The footprints of other components in this example

are listed in the Table 6. There should be at least one decoupling

capacitor per power pin. The decoupling capacitors should be

located as close as possible to the power pins. The layout as-

sumes that the board has clean analog power ground plane.

e

c

n

e

r

e

f

e

Re

z

i

S

2

C

,

1

C2

0

4

0

3

C5

0

8

0

8

C

,

7

C

,

6

C

,

5

C

,

4

C3

0

6

0

2

R3

0

6

0

s

e

z

i

s

t

n

e

n

o

p

m

o

c

s

t

s

il

,

6

e

l

b

a

T

:

E

T

O

N

.

e

l

p

m

a

x

e

t

u

o

y

a

l

s

i

h

t

n

i

n

w

o

h

s

ICS843002I-01

VCC

Logic Control Input Examples

C4

0.01u

R3

133

+

-

Optional Termination

R5

133

C7

0.1u

C8

0.1u

VCCA

VCCO

RU2

Not Install

Zo = 50 Ohm

Zo = 50 Ohm

Set Logic

Input to

'1'

R7

50

R4

82.5

C2

33pF

RD2

1K

Zo = 50 Ohm

C9

0.1u

R9

50

To Logic

Input

pins

R2

10

RD1

Not Install

U1

ICS843002i-01

VCC

R6

82.5

VCCO

+

-

18pF

X1

25 MHz

3.3V

VCC

VCC

C6

0.1u

VCC=3.3V

C3

10uF

C1

27pF

VCCO=3.3V

RU1

1K

To Logic

Input

pins

R8

50

Zo = 50 Ohm

Set Logic

Input to

'0'